LTC1062CSW datasheet(5/16 Pages) LINER

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LTC1062

1062fd

SWITCHED

CAPACITOR

NETWORK

CLOCK GEN

÷ 1, 2, 4

OSC

BOUT

OUT

V+

COSC

1062 BD

V–

AGND

fCLK

×1

BY CONNECTING PIN 4 TO V+, AGND OR V–, THE

OUTPUT FREQUENCY OF THE INTERNAL CLOCK

GENERATOR IS THE OSCILLATOR FREQUENCY DI-

VIDED BY 1, 2, 4. THE (fCLK/fC) RATIO OF 100:1 IS

WITH RESPECT TO THE INTERNAL CLOCK GENERA-

TOR OUTPUT FREQUENCY. PIN 5 CAN BE DRIVEN

WITH AN EXTERNAL CMOS LEVEL CLOCK. THE

LTC1062 CAN ALSO BE SELF-CLOCKED BY CON-

NECTING AN EXTERNAL CAPACITOR (COSC) TO

GROUND (OR TO V– IF COSC IS POLARIZED). UNDER

THIS CONDITION AND WITH ±5V SUPPLIES, THE

INTERNAL OSCILLATOR FREQUENCY IS:

fOSC ≅ 140kHz [33pF/(33pF + COSC)]

AC TEST CIRCUIT

AGND

V–

DIVIDER

RATIO

BOUT

OUT

V+

COSC

LTC1062

0.1µF

MEASURED

OUTPUT

0.1µF

1062 F01

C = 0.01µF

VIN

R = 25.8k

50Ω

–5V

fCLK = 100kHz

V– = –5V

R′

–

LTC1052

2πRC

FOR BEST MAX FLAT APPROXIMATION,

THE INPUT RC SHOULD BE SUCH AS:

A 0.5k RESISTOR, R′, SHOULD BE USED IF

THE BIPOLAR EXTERNAL CLOCK IS APPLIED

BEFORE THE POWER SUPPLIES TURN ON

1.63

fCLK

100

•

For Adjusting Oscillator Frequency, Insert a 50k Pot in Series with COSC. Use Two Times Calculated COSC

Figure 1

BLOCK DIAGRA

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