LTC2230UP datasheet(14/32 Pages) LINER

14 / 32 page

LTC2230/LTC2231

22301fb

PI FU CTIO S

CLKOUT–/CLKOUT+ (Pins 35 to 36): LVDS Data Valid

Output. Latch data on rising edge of CLKOUT–, falling edge

of CLKOUT+.

OF–/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output.

High when an over or under flow has occurred.

LVDS (Pin 57): Output Mode Selection Pin. Connecting

LVDS to 0V selects full rate CMOS mode. Connecting

LVDS to 1/3VDD selects demux CMOS mode with simulta-

neous update. Connecting LVDS to 2/3VDD selects demux

CMOS mode with interleaved update. Connecting LVDS to

VDD selects LVDS mode.

MODE (Pin 58): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Connecting MODE to 0V selects

offset binary output format and turns the clock duty cycle

stabilizer off. Connecting MODE to 1/3VDD selects offset

binary output format and turns the clock duty cycle stabi-

lizer on. Connecting MODE to 2/3VDD selects 2’s comple-

ment output format and turns the clock duty cycle stabi-

lizer on. Connecting MODE to VDD selects 2’s complement

output format and turns the clock duty cycle stabilizer off.

SENSE (Pin 59): Reference Programming Pin. Connecting

SENSE to VCM selects the internal reference and a ±0.5V

input range. VDD selects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±VSENSE. ±1V is the largest valid input range.

VCM (Pin 60): 1.6V Output and Input Common Mode Bias.

Bypass to ground with 2.2

μF ceramic chip capacitor.

GND (Exposed Pad) (Pin 65): ADC Power Ground. The

exposed pad on the bottom of the package needs to be

soldered to ground.

LTC2230UP Datasheet(PDF) 14 Page - Linear Technology