LTC2230UP datasheet(23/32 Pages) LINER

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LTC2230/LTC2231

22301fb

duty cycle. If the clock is turned off for a long period of

time, the duty cycle stabilizer circuit will require a hundred

clock cycles for the PLL to lock onto the input clock. To use

the clock duty cycle stabilizer, the MODE pin should be

connected to 1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2230/LTC2231 sample rate is

determined by droop of the sample-and-hold circuits. The

pipelined architecture of this ADC relies on storing analog

signals on small valued capacitors. Junction leakage will

discharge the capacitors. The specified minimum operat-

ing frequency for the LTC2230/LTC2231 is 1Msps.

Digital Output Modes

The LTC2230/LTC2231 can operate in several digital out-

put modes: LVDS, CMOS running at full speed, and CMOS

demultiplexed onto two buses, each of which runs at half

speed. In the demultiplexed CMOS modes the two buses

(referred to as bus A and bus B) can either be updated on

alternate clock cycles (interleaved mode) or simultaneously

(simultaneous mode). For details on the clock timing, refer

to the timing diagrams.

The LVDS pin selects which digital output mode the part

uses. This pin has a four-level logic input which should be

connected to GND, 1/3VDD, 2/3VDD or VDD. An external

resistor divider can be used to set the 1/3VDD or 2/3VDD

logic values. Table 2 shows the logic states for the

LVDS pin.

APPLICATIO S I FOR ATIO

DIGITAL OUTPUTS

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

D9 – D0

(2V Range)

(Offset Binary)

(2’s Complement)

>+1.000000V

11 1111 1111

01 1111 1111

+0.998047V

11 1111 1111

01 1111 1111

+0.996094V

11 1111 1110

01 1111 1110

+0.001953V

10 0000 0001

00 0000 0001

0.000000V

10 0000 0000

00 0000 0000

–0.001953V

01 1111 1111

11 1111 1111

–0.003906V

01 1111 1110

11 1111 1110

–0.998047V

00 0000 0001

10 0000 0001

–1.000000V

00 0000 0000

10 0000 0000

<–1.000000V

00 0000 0000

10 0000 0000

22301 F12a

ENC–

1.6V

VTHRESHOLD = 1.6V

ENC+

0.1

μF

LTC2230/

LTC2231

22301 F12b

ENC–

ENC+

130

3.3V

130

MC100LVELT22

LTC2230/

LTC2231

Figure 12a. Single-Ended ENC Drive,

Not Recommended for Low Jitter

Figure 12b. ENC Drive Using a CMOS to PECL Translator

LTC2230/LTC2231

22301 F13a

OVDD

VDD

0.1

μF

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 13a. Digital Output Buffer in CMOS Mode

Table 2. LVDS Pin Function

LVDS

Digital Output Mode

GND

Full-Rate CMOS

1/3VDD

Demultiplexed CMOS, Simultaneous Update

2/3VDD

Demultiplexed CMOS, Interleaved Update

VDD

LVDS

Digital Output Buffers (CMOS Modes)

Figure 13a shows an equivalent circuit for a single output

buffer in the CMOS output mode. Each buffer is powered

by OVDD and OGND, isolated from the ADC power and

ground. The additional N-channel transistor in the output

driver allows operation down to low voltages. The internal

resistor in series with the output makes the output appear

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