TLC4501, TLC4501A, TLC4502, TLC4502A

FAMILY OF SELF-CALIBRATING (Self-Cal

™)

PRECISION CMOS RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS

SLOS221A – MAY 1998 – REVISED JULY 1999

27

POST OFFICE BOX 655303

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using Microsim

Parts

™ Release 8, the model generation

software used with Microsim

PSpice

™. The Boyle macromodel (see Note 4) and subcircuit in Figure 46 are

information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most

cases):

NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”,

IEEE

Journal of Solid-State Circuits, SC-9, 353 (1974).

+

–

+

–

+

–

+

–

+

–

.subckt TLC4501 1 2 3 4 5

*

c1

11

12

1.4559E–12

c2

6

7

8.0000E–12

css

10

99

1.0000E–30

dc

5

53

dy

de

54

5

dy

dlp

90

91

dx

dln

92

90

dx

dp

4

3

dx

egnd

99

0

poly(2) (3,0) (4,0) 0 .5 .5

fb

7

99

poly(5) vb vc ve vlp vln 0

+ 84.657E9 –1E3 1E3 85E9 –85E9

ga

6

0

11 12 236.25E–6

gcm

0

6

10 99 2.3625E–9

iss

10

4

dc 20.000E–6

hlim

90

0

vlim 1K

j1

11

2

10 jx1

j2

12

1

10 jx2

r2

6

9

100.00E3

rd1

3

11

4.2328E3

rd2

3

12

4.2328E3

ro1

8

5

5.0000E–3

ro2

7

99

5.0000E–3

rp

3

4

5.0000E3

rss

10

99

10.000E6

vb

9

0

dc 0

vc

3

53

dc .92918

ve

54

4

dc .82918

vlim

7

8

dc 0

vlp

91

0

dc 67

vln

0

92

dc 67

.model dx D(Is=800.00E–18)

.model dy D(Is=800.00E–18 Rs=1m Cjo=10p)

.model jx1 NJF(Is=500.00E–15 Beta=2.7907E–3 Vto=–1)

.model jx2 NJF(Is=500.00E–15 Beta=2.7907E–3 Vto=–1)

.ends

VDD +

RP

IN –

2

IN +

1

VDD –

RD1

11

J1

J2

10

RSS

ISS

3

12

RD2

DP

VD

DC

4

C1

53

EGND

FB

HLIM

90

DLP

91

DLN

92

VLN

VLP

99

CSS

+

–

VE

DE

54

OUT

+

–

+

–

R2

6

9

VB

C2

GA

VLIM

8

5

RO1

RO2

7

GCM

Figure 46. Boyle Macromodel and Subcircuit

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