TMS320C32PCM datasheet(16/44 Pages) TI

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TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts

To reduce external logic and simplify the interface, the external interrupts can be either edge- or level-triggered.

Unlike the fixed interrupt-trap vector-table location of the TMS320C30 and TMS320C31 devices, the

TMS320C32 has a user-relocatable interrupt-trap vector table. The interrupt-trap vector table must start on a

256-word boundary. Figure 10 shows the interrupt and trap vector locations memory mapping with shading to

indicate reserved areas. The reset vector is fixed to address 0h as shown in Figure 8.

EA (ITTP) + 3Fh

EA (ITTP) + 3Eh

EA (ITTP) + 3Dh

EA (ITTP) + 3Ch

EA (ITTP) + 3Bh

EA (ITTP) + 20h

TRAP0

EA (ITTP) + 1Fh

EA (ITTP) + 0Dh

DINT1

EA (ITTP) + 0Ch

DINT0

EA (ITTP) + 0Bh

TINT1

EA (ITTP) + 0Ah

TINT0

EA (ITTP) + 09h

EA (ITTP) + 08h

EA (ITTP) + 07h

RINT0

EA (ITTP) + 06h

XINT0

EA (ITTP) + 05h

INT3

EA (ITTP) + 04h

INT2

EA (ITTP) + 03h

INT1

EA (ITTP) + 02h

INT0

EA (ITTP) + 01h

EA (ITTP) + 00h

TRAP31

TRAP30

TRAP29

TRAP28

TRAP27

Reserved

Figure 10. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations

TMS320C32PCM Datasheet(PDF) 16 Page - Texas Instruments

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