TMS320VC5402 datasheet(41/68 Pages) TI

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TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a

memory write

(MSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 14)

PARAMETER

MIN

MAX

UNIT

td(CLKH-A)

Delay time, CLKOUT high to address valid‡

–2

td(CLKL-A)

Delay time, CLKOUT low to address valid§

–2

td(CLKL-MSL)

Delay time, CLKOUT low to MSTRB low

–1

td(CLKL-D)W

Delay time, CLKOUT low to data valid

td(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high

–1

td(CLKH-RWL)

Delay time, CLKOUT high to R/W low

–1

td(CLKH-RWH)

Delay time, CLKOUT high to R/W high

–1

td(RWL-MSTRBL)

Delay time, R/W low to MSTRB low

H – 2

H + 1

th(A)W

Hold time, address valid after CLKOUT high‡

th(D)MSH

Hold time, write data valid after MSTRB high

H–3

H+6§

tw(SL)MS

Pulse duration, MSTRB low

2H–2

tsu(A)W

Setup time, address valid before MSTRB low

2H–2

tsu(D)MSH

Setup time, write data valid before MSTRB high

2H–6

2H+5§

ten(D–RWL)

Enable time, data bus driven after R/W low

H–5

tdis(RWH–D)

Disable time, R/W high to data bus high impedance

† Address, PS, and DS timings are all included in timings referenced as address.

‡ In the case of a memory write preceded by a memory write

§ In the case of a memory write preceded by an I/O cycle

TMS320VC5402 Datasheet(PDF) 41 Page - Texas Instruments

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