TMS320VC5409GGU datasheet(59/89 Pages) TI

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Documentation Support

April 1999 − Revised February 2004

SPRS082E

5.7.3

Parallel I/O Port Read

Table 5−9 and Table 5−10 assume testing over recommended operating conditions, IOSTRB = 0, and

H = 0.5tc(CO) (see Figure 5−7).

Table 5−9. Parallel I/O Read Port Timing Requirements†

MIN

MAX

UNIT

ta(A)IO

Access time, read data access from address valid‡

3H−9

ta(ISTRBL)IO

Access time, read data access from IOSTRB low‡

2H−8

tsu(D)IOR

Setup time, read data before CLKOUT high

th(D)IOR

Hold time, read data after CLKOUT high

th(ISTRBH-D)R

Hold time, read data after IOSTRB high

† Address and IS timings are included in timings referenced as address.

‡ This access timing reflects a zero wait-state timing.

Table 5−10. Parallel I/O Port Read Switching Characteristics†

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid

td(CLKH-ISTRBL)

Delay time, CLKOUT high to IOSTRB low

td(CLKH-ISTRBH)

Delay time, CLKOUT high to IOSTRB high

th(A)IOR

Hold time, address after CLKOUT low

† Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

D[15:0]

A[22:0]

CLKOUT

th(A)IOR

td(CLKH-ISTRBH)

th(D)IOR

tsu(D)IOR

ta(A)IO

td(CLKH-ISTRBL)

td(CLKL-A)

ta(ISTRBL)IO

th(ISTRBH-D)R

NOTE A: A[22:16] apply to DMA accesses to extended I/O, DATA, PROGRAM memory. The CPU has access to only extended

PROGRAM memory.

Figure 5−7. Parallel I/O Port Read

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