TMS320VC5409GGU datasheet(27/89 Pages) TI

27 / 89 page

Functional Overview

April 1999 − Revised February 2004

SPRS082E

Table 3−7. Pin Control Register (PCR) Bit Field Description

BIT

NAME

FUNCTION

15 – 14

Reserved

Reserved. Pins are not used.

XIOEN

Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2)

XIOEN = 0

DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os.

XIOEN = 1

DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These serial port

pins do not perform serial port operations.

RIOEN

Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2)

RIOEN = 0

DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not general-purpose

I/Os.

RIOEN = 1

DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose I/Os.

These serial port pins do not perform serial port operations. The CLKS pin is affected by a

combination of RRST and RIOEN signals of the receiver.

FSXM

Transmit frame synchronization mode

FSRM = 0

Frame synchronization signal derived from an external source.

FSRM = 1

Frame synchronization is determined by the sample rate generator frame synchronization mode

bit (FSGM) in the SRGR2.

FSRM

Receive frame synchronization mode

FSRM = 0

Frame synchronization pulses generated by an external device. FSR is an input pin.

FSRM = 1

Frame synchronization generated internally by the sample rate generator. FSR is an output pin

except when GSYNC=1 in the SRGR.

CLKXM

Transmitter clock mode

CLKXM = 0

Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input pin

CLKXM= 1

CLK(R/X) is an output pin and is driven by the internal sample rate generator

During SPI mode (CLKSTP is a non-zero value):

CLKXM = 0

McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR is

internally driven by CLKX.

CLKXM= 1

McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR) and the

shift clock of the SPI-compliant slaves in the system.

CLKRM

Receiver clock mode

Case 1: Digital loop-back mode is not set (DLB=0) in SPCR1.

CLKRM = 0

Receive clock (CLKR) is an input pin driven by an external clock.

CLKRM= 1

CLKR is an output pin and is driven by the internal sample rate generator

Case 2: Digital loop-back mode set (DLB=1) in SPCR1

CLKRM = 0

Receive clock (Not the CLKR pin) is driven by transmit clock (CLKX), which is based on CLKXM

bit in the PCR. CLKR pin is in high-impedance mode.

CLKRM= 1

CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based

on the CLKXM bit in the PCR.

SCLKME

Sample rate clock mode extended

SCLKME = 0

External clock via CLKS or CPU clock is used as a reference by the sample rate generator.

SCLKME = 1

External clock via CLKR or CLKX clock is used as a reference by the sample rate generator.

CLKS STAT

CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input.

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