TMS370CX2XFN datasheet(16/60 Pages) TI

16 / 60 page

TMS370Cx2x

8-BIT MICROCONTROLLER

SPNS018C – FEBRUARY 1993 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

privileged operation and EEPROM write-protection override (continued)

Table 9. Privileged Bits

CONTROL BIT

NAME

LOCATION

CONTROL BIT

SCCR0

P010.5

P010.6

PF AUTO WAIT

OSC POWER

SCCR1

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN/IDLE

HALT/STANDBY

SCIPRI

P05F.4

P05F.5

P05F.6

SCI ESPEN

SCI RX PRIORITY

SCI TX PRIORITY

SCI STEST

T1PRI

P04F.6

P04F.7

T1 PRIORITY

T1 STEST

SPIPRI

P03F.5

P03F.6

P03F.7

SPI ESPEN

SPI PRIORITY

SPI STEST

† The privileged bits are shown in a bold typeface in Table 11.

The WPO mode provides an external hardware method of overriding the WPR of data EEPROM on the

TMS370Cx2x. WPO mode is entered by applying a 12-V input to the MC pin after the RESET pin input goes

high. The high voltage on the MC pin during the WPO mode is not the programming voltage for the data

EEPROM or program EPROM. All EEPROM programming voltages are generated on-chip. The WPO mode

provides hardware system level capability to modify the personality or calibration information in the data

EEPROM while the device remains in the application, but only while a 12-V external input is present on the MC

pin (normally not available in the end application except in a service or diagnostic environment).

low-power operating modes

The TMS370Cx2x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact when

the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The

HALT / STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops;

however, the oscillator, internal clocks, timer 1, and receive start-bit detection circuit of the SCI1 remain active.

System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1, INT2,

INT3, timer 1 interrupt, or low level on the receive pin of the SCI1) is detected.

In the HALT mode (HALT / STANDBY = 1), the TMS370Cx2x is in its lowest power consumption mode. The

oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is suspended

until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level on the

receive pin of the SCI1) is detected. The power-down mode-selection bits are summarized in Table 10.

TMS370CX2XFN Datasheet(PDF) 16 Page - Texas Instruments

TMS370CX2XFN Datasheet(HTML) 16 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL