TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997

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POST OFFICE BOX 1443

The TMS370C732 device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing

through location 7FFFh as shown in Figure 3. Reading the program EPROM modules is identical to reading

other internal memory. During programming, the EPROM is controlled by the EPROM control register

(EPCTLL). The program EPROM module features include:

–

–

Control register: EPROM programming is controlled by the EPROM control register (EPCTLL) located

in the peripheral file (PF) frame at location P01C as shown in Table 5.

–

Reset: All programming to the EPROM module is halted

–

Low-power modes

–

13 V not applied to MC

The program ROM consists of 8K bytes of mask programmable read-only memory. The program ROM is used

for permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device

fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx32 CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

generated internally, while one (RESET pin) is controlled externally. These actions are as follows:

key register, or if the re-initialization does not occur before the watchdog timer timeout . See the

TMS370

Family User’s Guide (literature number SPNU127) for more information.

See the

TMS370 Family User’s Guide (literature number SPNU127) for more information.

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x32 device to reset external system components. Additionally, if a cold start condition

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4) and the cold-start flag

(COLD START, SCCR0.7) to determine the source of the reset. A reset does not clear these flags. Table 6

depicts the reset sources. If none of the sources indicated in Table 1 caused the reset, then the RESET pin was

pulled low by the external hardware or the PACT module’s watchdog.

† Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments, and 7FECh through 7FFFh are reserved for interrupt and reset

vectors. Trap vectors, used with TRAP0 through TRAP15 instructions are located between addresses 7FC0h and 7FDFh. PACT interrupts are

located between addresses 7F9Ch and 7FBFh.