TMS370CX32 datasheet(16/43 Pages) TI

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TMS370Cx32

8-BIT MICROCONTROLLER

SPNS015C – FEBRUARY 1990 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

low-power and IDLE modes (continued)

Table 9. Low-Power / Idle Control Bits

POWER-DOWN CONTROL BITS

PWRDWN / IDLE

(SCCR2.6)

HALT / STANDBY

(SCCR2.7)

MODE SELECTED

STANDBY

HALT

X †

IDLE

† X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6-7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method for always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This

means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (SP, PC, and ST), I / O pin direction and output data, and status registers of all on-chip peripheral

functions. Since all CPU instruction processing is stopped during the STANDBY and HALT modes, the clocking

of the WD timer is inhibited.

clock modules

The ’x32 family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and

divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the

manufacturing process of a TMS370 microcontroller. The ’x32 masked-ROM devices offer both options to meet

system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’732A

EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a one-to-one match of the external resonator frequency (CLKIN) to the internal system

clock (SYSCLK) frequency, whereas the divide-by-4 produces a SYSCLK which is one-fourth the frequency of

the external resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by

four, and the clock module then divides the resulting signal by four to provide the four-phased internal system

clock signals. The resulting SYSCLK is equal to the resonator frequency. These are formulated as follows:

Divide-by-4 option : SYSCLK

external resonator frequency

+ CLKIN

Divide-by-1 option : SYSCLK

external resonator frequency

+ CLKIN

The main advantage of choosing a divide-by-1 oscillator is the reduced EMI. The harmonics of low-speed

resonators extend through fewer of the emissions spectrum than the harmonics of faster resonators. The

divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper

decay of emissions produced by the oscillator.

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