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LTC4160/LTC4160-1

41601f

APPLICATIONS INFORMATION

This same current pulse must not raise VBUS any higher

than 2V when connected to a standard host which must

have at least 96μF. The 96μF for a standard host represents

the minimum capacitance with VBUS between 4.75V and

5.25V. Since the SRP pulse must not drive VBUS greater

than 2V, the capacitance seen at these voltage levels can be

greater than 96μF, especially if MLCCs are used. Therefore,

the 96μF represents a lower bound on the standard host

bypass capacitance for determining the amplitude and

duration of the current pulse. More capacitance will only

decrease the maximum level that VBUS will rise to for a

given current pulse.

Figure 9 shows an On-The-Go device using the LTC4160/

LTC4160-1 acting as the A device. Additional capacitance

can be placed on the VBUS pin of the LTC4160/LTC4160-

1 when using the overvoltage protection circuit. The B

device may not be able to distinguish between a powered

down LTC4160/LTC4160-1 with overvoltage protection

and a powered down standard host because of this extra

capacitance. In addition, if the SRP pulse raises VBUS

above its UVLO threshold of 4.3V the LTC4160/LTC4160-1

will assume input power is available and will not attempt

to drive VBUS. Therefore, it is recommended that an On-

The-Go device using the LTC4160/LTC4160-1 respond to

data-line pulsing.

When an On-The-Go device using the LTC4160/LTC4160-1

becomes the B device, as in Figure 10, it must send out

a data line pulse followed by a VBUS pulse to request a

session from the A device. The On-The-Go device designer

can choose how much capacitance will be placed on the

VBUS pin of the LTC4160/LTC4160-1 and then generate

a VBUS pulse that can distinguish between a powered

down On-The-Go A device and a powered down standard

host. A suitable pulse can be generated because of the

disparity in the bypass capacitances of an On-The-Go A

device and a standard host even if there is somewhat more

than 6.5μF capacitance connected to the VBUS pin of the

LTC4160/LTC4160-1.

Board Layout Considerations

The Exposed Pad on the backside of the LTC4160/

LTC4160-1 package must be securely soldered to the PC

board ground. This is the primary ground pin in the pack-

age, and it serves as the return path for both the control

circuitry and N-channel MOSFET switch.

Furthermore, due to its high frequency switching circuitry,

it is imperative that the input capacitor, inductor, and output

capacitor be as close to the LTC4160/LTC4160-1 as pos-

sible and that there be an unbroken ground plane under the

LTC4160/LTC4160-1 and all of its external high frequency

components. High frequency current, such as the VBUS

current tends to ﬁnd its way on the ground plane along a

mirror path directly beneath the incident path on the top

of the board. If there are slits or cuts in the ground plane

due to other traces on that layer, the current will be forced

to go around the slits. If high frequency currents are not

allowed to ﬂow back through their natural least-area path,

excessive voltage will build up and radiated emissions will

occur (see Figure 11). There should be a group of vias

directly under the grounded backside leading directly

down to an internal ground plane. To minimize parasitic

inductance, the ground plane should be as close as pos-

sible to the top plane of the PC board (layer 2).

Figure 9. LTC4160/LTC4160-1 as the A Device

ON-THE-GO

POWER

MANAGER

ON-THE-GO

TRANSCEIVER

B DEVICE

41601 F11

A DEVICE

D+

D–

OVSENS

OVGATE

VBUS

<6.5μF

WITHOUT OVP

OVP

(OPTIONAL)

ON-THE-GO

TRANSCEIVER

LTC4160/

LTC4160-1

ENOTG

LTC4160EPDC Datasheet(PDF) 26 Page - Linear Technology

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