ADC

ADC

ADC

ADC

ADC

AS1419

AS1419A

AS1419 & AS1419A

Rev. 1.5 08/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

8

Austin Semiconductor, Inc.

CONVERSION DETAILS

The AS1419 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an analog

signal to a 14-bit parallel output. The ADC is complete with a

precision reference and an internal clock. The control logic

provides easy interface to microprocessors and DSPs (please

refer to Digital Interface section for the data format).

Conversion start is controlled by the CS\ and CONVST\

inputs. At the start of the conversion, the successive

approximation register (SAR) is reset. Once a conversion cycle

has begun, it cannot be restarted.

During the conversion, the internal differential 14-bit

capacitive DAC output is sequenced by the SAR from the most

significant bit (MSB) to the least significant bit (LSB).

Referring to Figure 1, the +A

IN

and –A

IN

inputs are connected

to the sample-and-hold capacitors (C

SAMPLE

) during the

acquire phase and the comparator offset is nulled by the zero-

ing switches. In this acquire phase, a minimum delay of 200ns

will provide enough time for the sample-and-hold capacitors to

acquire the analog signal. During the convert phase, the

comparator zeroing switches open, putting the comparator into

compare mode. The input switches the C

SAMPLE

capacitors to

ground, transferring the differential analog input charge onto

the summing junction. This input charge is successively com-

pared with the binary weighted charges supplied by the differ-

ential capacitive DAC. Bit decisions are made by the high speed

comparator. At the end of a conversion, the differential DAC

output balances the +A

IN

and –A

IN

input charges. The SAR

contents (a 14-bit data word) which represents the difference of

+AIN and –AIN are loaded into the 14-bit output latches.

FIGURE 1: Simplified Block Diagram

DYNAMIC PERFORMANCE

The AS1419 has excellent high speed sampling capability.

FFT (Fast Fourier Transform) test techniques are used to test

the ADC’s frequency response, distortion and noise at the rated

throughput. By applying a low distortion sine wave and

analyzing the digital output using an FFT algorithm, the ADC’s

spectral content can be examined for frequencies outside the

fundamental. Figure 2 shows a typical AS1419 FFT plot.