MPC82X52AS datasheet(49/72 Pages) MEGAWIN

49 / 72 page

MEGAWIN

MPC82x52A Data Sheet

Set the clock rate of the SPI as the frequency of the clock source over 64.

{1,1} :=

Set the clock rate of the SPI as the frequency of the clock source over 128.

There are two extra SFRs make relation with SPI application.

SFR: SPIDAT (SPI Data register)

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

Data to be transmitted or Data received

The SFR SPIDAT holds the data to be transmitted or the data received.

SFR: SPISTAT (SPI Status register)

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

SPIF

WCOL

SPIF := SPI transfer completion flag.

When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if both the

ESPI (IE.5) bit and the EA (IE.7) bit are set. If SS is an input and is driven low when SPI is

in master mode with SSIG=0, SPIF will also be set to signal the “mode change”. The SPIF

is cleared in software by “writing 1 to this bit”.

WCOL := SPI Write Collision flag

The WCOL bit is set if the SPI data register SPIDAT is written during a data transfer. The

WCOL flag is cleared in software by “writing 1 to this bit”.

Configure the device to Master/Slave mode

SPEN SSIG

MSTR

Mode

MISO

MOSI SPICLK

Remark

SPI disable

GPI/O GPI/O GPI/O

SPI is disabled.

Active Salve

output input

input

Selected as slave

InActive Slave

Hi-Z

input

Not selected.

1→0

slave

output input

input

Convert from Master to

Slave

Master

input

output output

SPICLK depends on CPOL

Slave

output input

input

Slave

Master

input

output output

Master

MPC82x52AS Datasheet(PDF) 49 Page - Megawin Technology Co., Ltd

MPC82x52AS Datasheet(HTML) 49 Page - Megawin Technology Co., Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL