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MB91F467DA Datasheet(PDF) 34 Page - fujitsu semiconductor |
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MB91F467DA Datasheet(HTML) 34 Page - fujitsu semiconductor |
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34 / 140 page  MB91460D Series 34 DS07-16612-2E 3.2. Flash access timing settings in CPU mode The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or maximum clock modulation) for Flash read and write access. 3.2.1. Flash read timing settings (synchronous read) 3.2.2. Flash write timing settings (synchronous write) Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark to 24 MHz 0 0 0 - 1 to 48 MHz 0 0 1 - 2 to 96 MHz 1 1 3 - 4 to 100 MHz 1 1 3 - 4 not available on MB91F467Dx Core clock (CLKB) ATD ALEH EQ WEXH WTC Remark to 32 MHz 1 - - 0 4 to 48 MHz 1 - - 0 5 to 64 MHz 1 - - 0 6 to 96 MHz 1 - - 0 7 to 100 MHz 1 - - 0 7 not available on MB91F467Dx |
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