SC9RS08KA2 datasheet(23/134 Pages) FREESCALE

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Chapter 3 Modes of Operation

SC9RS08KA2 Series Data Sheet, Rev. 1

Freescale Semiconductor

Table 3-1 summarizes the behavior of the MCU in wait mode.

3.6

Stop Mode

Stop mode is entered upon execution of a STOP instruction when the STOPE bit in the system option

not set when the CPU executes a STOP instruction, the MCU will not enter stop mode and an illegal

opcode reset is forced.

Table 3-2 summarizes the behavior of the MCU in stop mode.

Upon entering stop mode, all of the clocks in the MCU are halted. The ICS is turned off by default when

the IREFSTEN bit is cleared and the voltage regulator is put in standby. The states of all of the internal

registers and logic, as well as the RAM content, are maintained. The I/O pin states are held.

Exit from stop is done by asserting RESET, any asynchronous interrupt that has been enabled, or the

real-time interrupt. The asynchronous interrupts are the KBI pins, LVD interrupt, or the ACMP interrupt.

If stop is exited by asserting the RESET pin, the MCU will be reset and program execution starts at

location $3FFD. If exited by means of an asynchronous interrupt or real-time interrupt, the next instruction

after the location where the STOP instruction was executed will be executed accordingly. It is the

responsibility of the user program to probe for the corresponding interrupt source that woke the CPU.

A separate self-clocked source (

≈1 kHz) for the real-time interrupt allows a wakeup from stop mode with

no external components. When RTIS = 000, the real-time interrupt function and the 1-kHz source are

disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case, the real-time

interrupt cannot wake the MCU from stop.

The trimmed 32-kHz clock in the ICS module can also be enabled for the real-time interrupt to allow a

wakeup from stop mode with no external components. The 32-kHz clock reference is enabled by setting

Table 3-1. Wait Mode Behavior

Mode

CPU

Digital

Peripherals

ICS

ACMP

Regulator

I/O Pins

RTI

Wait

Standby

Optionally on

Optionally

States held

Optionally on

Table 3-2. Stop Mode Behavior

Mode

CPU

Digital

Peripherals

ICS1

1 ICS requires IREFSTEN = 1 and LVDE and LVDSE must be set to allow operation in stop.

ACMP2

2 If bandgap reference is required, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering

stop.

Regulator

I/O Pins

RTI3

3 If the 32-kHz trimmed clock in the ICS module is selected as the clock source for the RTI, LVDE and LVDSE bits

in the SPMSC1 must both be set before entering stop.

Stop

Standby

Optionally

Standby

States held

Optionally on

SC9RS08KA2 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc

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