IKCS12F60B2C datasheet(7/18 Pages) INFINEON

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CIPOS™ IKCS12F60B2A

IKCS12F60B2C

Data Sheet

7/18

Rev. 2.2, March 2009

A minimum deadtime insertion of typ 380ns is also

provided, in order to reduce cross-conduction of

the external power switches.

TEMP (temperature NTC, Pin 24)

The TEMP terminal provides direct access to the

NTC, which is referenced to VSS. An external

pull-up resistor connected to +5V ensures, that

the resulting voltage can be directly connected to

the microcontroller.

RNTC

TEMP

CIPOS™

VSS

Figure 3: Internal Circuit at pin TEMP

ITRIP (Over-current detection function, Pin 21)

CIPOS™ provides an over-current detection

function by connecting the ITRIP input with the

motor current feedback. The ITRIP comparator

threshold (typ 0.46V) is referenced to VSS

ground. A input noise filter (typ: tITRIPMIN = 225ns)

prevents the driver to detect false over-current

events.

Over-current detection generates a hard shut

down of all outputs of the gate driver after the

shutdown propagation delay of typically 900ns.

The fault-clear time is set to typically to 4.7ms.

VDD, VSS (control side supply and reference,

Pin 22, 23)

VDD is the low side supply and it provides power

both to input logic and to low side output power

stage. Input logic is referenced to VSS ground as

well as the under-voltage detection circuit.

The under-voltage circuit enables the device to

operate at power on when a supply voltage of at

least a typical voltage of VDDUV+ = 12.1 V is at

least present.

The IC shuts down all the gate drivers power

outputs, when the VCC supply voltage is below

VDDUV- = 10.4 V. This prevents the external power

switches from critically low gate voltage levels

during on-state and therefore from excessive

power dissipation.

VB1,2,3 and VS1,2,3 (High side supplies, Pin 1,

2, 4, 5, 7, 8)

VB to VS is the high side supply voltage. The high

side circuit can float with respect to VSS following

the

external

high

side

power

device

emitter/source voltage.

Due to the low power consumption, the floating

driver stage is supplied by an integrated bootstrap

circuit connected to VDD. This includes also

integrated bootstrap capacitors of 100 nF at each

floating supply, which are located very close to the

gate drive circuit.

The under-voltage detection operates with a rising

supply threshold of typical VBSUV+ = 12.1 V and a

falling threshold of VDDUV- = 10.4 V according to

Figure 4.

VS1,2,3 provide a high robustness against

negative voltage in respect of VSS of -50 V. This

ensures very stable designs even under rough

conditions.

VRU, VRV, VRW (low side emitter, Pin 12, 13,

14)

The low side emitters are available for current

measurements

each

phase

leg.

recommended to keep the connection to pin VSS

as short as possible in order to avoid unnecessary

inductive voltage drops.

V+ (positive bus input voltage, Pin 10)

The high side IGBT are connected to the bus

voltage. It is recommended, that the bus voltage

does not exceed 500 V.

Figure 4: Input filter timing diagram

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