ICS8430-62 datasheet(16/23 Pages) IDT

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ICS8430-62 Datasheet

500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

ICS8430AY-62 REVISION A JULY 2, 2009

The following component footprints are used in this layout example.

All the resistors and capacitors are size 0603.

Power and Grounding

Place the decoupling capacitors C14 and C15, as close as possible

to the power pins. If space allows, placement of the decoupling

capacitor on the component side is preferred. This can reduce

unwanted inductance between the decoupling capacitor and the

power pin caused by the via.

Maximize the pad size of the power (ground) at the decoupling

capacitor. Maximize the number of vias between power (ground) and

the pads. This can reduce the inductance between the power

(ground) plane and the component power (ground) pins.

If VCCA shares the same power supply with VCC, insert the RC filter

R7, C11, and C16 in between. Place this RC filter as close to the

VCCA pin as possible.

Clock Traces and Termination

The component placements, locations and orientations should be

arranged to achieve the best clock signal quality. Poor clock signal

quality can degrade the system performance or cause system failure.

In the synchronous high-speed digital system, the clock signal is less

tolerable to poor signal quality than other signals. Any ringing on the

rising or falling edge or excessive ring back can cause system failure.

The trace shape and the trace delay might be restricted by the

available space on the board and the component location. While

routing the traces, the clock signal traces should be routed first and

should be locked prior to routing other signal traces.

• The traces with 50

Ω transmission lines TL1 and TL2 at

FOUT and nFOUT should have equal delay and run adjacent to

each other. Avoid sharp angles on the clock trace.Sharp angle

turns cause the characteristic impedance to change on the

transmission lines.

• Avoid sharp angles on the clock trace. Sharp angle turns

cause the characteristic impedance to change on the

transmission lines.

• Keep the clock trace on the same layer. Whenever possible,

avoid any vias on the clock traces. Any via on the trace can

affect the trace characteristic impedance and hence degrade

signal quality.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow more space between the clock trace and

the other signal trace.

• Make sure no other signal traces are routed between the

clock trace pair.

The matching termination resistors R1, R2, R3 and R4 should be

located as close to the receiver input pins as possible. Other

termination schemes can also be used but are not shown in this

example.

Crystal

The crystal X1 should be located as close as possible to the pins 24

(XTAL_OUT) and 25 (XTAL_IN). The trace length between the X1

and U1 should be kept to a minimum to avoid unwanted parasitic

inductance and capacitance. Other signal traces should not be

routed near the crystal traces.

Figure 7B. PCB Board Layout for ICS8430-62

TL1, TL21N are 50 Ohm

traces and equal length

C16

PIN 1

C11

C14

TL1

C15

VIA

Close to the input

pins of the

receiver

GND

TL1N

VCCA

VCC

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