TLE7263E datasheet(6/63 Pages) INFINEON

6 / 63 page

Data Sheet

Rev. 1.51, 2007-06-22

TLE 7263E

Pin Configuration

4LIN

LIN Bus; Bus Line for the LIN interface, according to

ISO 9141 and LIN specification 1.3 and 2.0

DISPI

SPI Data Input; receives serial data from the control device;

serial data transmitted to DI is a 16-bit control word with the

Least Significant Bit (LSB) transferred first: the input has a

pull-down and requires CMOS logic level inputs; DI will

accept data on the falling edge of CLK-signal

DOSPI

SPI Data Output; this tri-state output transfers diagnosis

data to the control device; the output will remain 3-stated

unless the device is selected by a low on Chip-Select-Not

(CSN)

CLKSPI

SPI Clock Input; clock input for shift register; CLK has an

internal pull-down and requires CMOS logic level inputs

CSNSPI SPI Chip Select Not Input; CSN is an active low input; serial

communication is enabled by pulling the CSN terminal low;

CSN input should only be transitioned when CLK is low; CSN

has an internal pull-up and requires CMOS logic level inputs

OUTHS High Side Switch Output; controlled via SPI, in SBC Sleep

Mode controlled by internal cyclic sense function when

selected

TxDCAN CAN Transmit Data Input; integrated pull-up

RxDCAN CAN Receive Data Output

SPLIT

CAN Termination Output; to support the recessive voltage

level of the bus lines

CANH

CAN High Line Output

CANL

CAN Low Line Input

STS

Send-to-Sleep; to switch the SBC back into low current

mode during cyclic wake

1, 2,

6,14,

18,19,

23,36

GND

Ground

3NC

Not Connected Internally; leave open or connect to GND

Exposed Pad; internally connected to GND; connect to

GND on board

Table 1

Pin Definitions and Functions (cont’d)

Symbol Function

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