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TLE8261E Datasheet(PDF) 73 Page - Infineon Technologies AG |
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TLE8261E Datasheet(HTML) 73 Page - Infineon Technologies AG |
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73 / 82 page ![]() Data Sheet 73 Rev. 1.0, 2009-03-31 TLE8261E Serial Peripheral Interface Figure 35 SPI Timing Diagram Note: Numbers in drawing correlate to the last 2 digits of the Pos. number in the Electrical Characteristics table. 14.7.20 Input Signal Rise Time at pin SDI, CLK and CSN t rIN – – 50 ns – 14.7.21 Input Signal Fall Time at pin SDI, CLK and CSN t fIN – – 50 ns – 14.7.22 Delay Time for Mode Change from Normal Mode to Sleep Mode t fIN –– 10 µs – 14.7.23 CSN High Time t CSN(high) 10 – – µs - Data Output Timing 1) 14.7.24 SDO Rise Time t rSDO –30 80 ns CL = 100 pF 14.7.25 SDO Fall Time t fSDO –30 80 ns CL = 100 pF 14.7.26 SDO Enable Time t ENSDO – – 50 ns low impedance 14.7.27 SDO Disable Time t DISSDO – – 50 ns high impedance 14.7.28 SDO Valid Time t VASDO – – 60 ns CL = 100 pF 1) Not subject to production test; specified by design 14.7 Electrical Characteristics (cont’d) V S = 5.5 V to 28 V; Tj = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Pos. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. CSN CLK DI DO 13 12 not defined LSB MSB Flag LSB MSB 15 26 28 18 16 27 23 19 14 17 |
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