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AT89LP213 Datasheet(PDF) 87 Page - ATMEL Corporation |
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AT89LP213 Datasheet(HTML) 87 Page - ATMEL Corporation |
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87 / 98 page  87 3538D–MICRO–10/09 AT89LP213/214 Figure 24-16. SPI Slave Timing (CPHA = 1) Figure 24-17. Shift Register Mode Timing Waveform SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI t SCK t SSE t SHSL t SHSL t SLSH t SLSH t SSD t SIH t SIS t SOE t SOV t SOH t SOX t SF t SR 24.6 Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for V CC = 2.4V to 5.5V and Load Capacitance = 80 pF. Symbol Parameter Variable Oscillator Units Min Max tXLXL Serial Port Clock Cycle Time 2tCLCL -15 µs t QVXH Output Data Setup to Clock Rising Edge t CLCL -15 ns t XHQX Output Data Hold after Clock Rising Edge t CLCL -15 ns tXHDX Input Data Hold after Clock Rising Edge 0 ns t XHDV Input Data Valid to Clock Rising Edge 15 ns 01 2 3 4 5 6 7 VALID VALID VALID VALID VALID VALID VALID VALID CLOCK WRITE TO SBUF OUTPUT DATA CLEAR RI INPUT DATA |
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