AT89LP213 datasheet(31/98 Pages) ATMEL

31 / 98 page

3538D–MICRO–10/09

AT89LP213/214

14.4

Mode 3 – 8-bit Split Timer

Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in

Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is

shown in Figure 14-4. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0, and TF0. TH0 is

locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1

from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. While Timer 0 is in Mode 3, Timer 1

will still obey its settings in TMOD but cannot generate an interrupt.

Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the

AT89LP213/214 can appear to have three Timer/Counters. When Timer 0 is in Mode 3, Timer 1

can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can

still be used by the serial port as a baud rate generator or in any application not requiring an

interrupt.

Figure 14-4. Timer/Counter 0 Mode 3: Two 8-bit Counters

Note:

RH0/RL0 are not required by Timer 0 during Mode 3 and may be used as temporary storage

registers.

Control

Interrupt

Control

Interrupt

(8 Bits)

C/T = 0

C/T =1

T0 Pin

GATE

INT0 Pin

÷TPS

Table 14-1.

TCON

– Timer/Counter Control Register

TCON = 88H

Reset Value = 0000 0000B

Bit Addressable

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

543

Symbol

Function

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors

to interrupt routine.

TR1

Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors

to interrupt routine.

TR0

Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.

IE1

Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.

IT1

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

IE0

Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.

IT0

Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

AT89LP213 Datasheet(PDF) 31 Page - ATMEL Corporation

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