ATtiny261A datasheet(105/292 Pages) ATMEL

105 / 292 page

105

8197A–AVR–10/09

ATtiny261A/461A/861A

Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclkT1/8)

Figure 12-18 shows the setting of TOV1 in Phase and Frequency Correct PWM Mode.

Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8)

12.10 Fault Protection Unit

The Timer/Counter1 incorporates a Fault Protection unit, which can be set to disable the PWM

output pins when an external event is triggered. The external signal indicating an event can be

applied via the external interrupt INT0 pin or, alternatively, via the analog-comparator unit. The

Fault Protection unit is illustrated in Figure 12-19. The elements of the block diagram that are not

directly a part of the Fault Protection unit are gray shaded.

Figure 12-19. Fault Protection Unit Block Diagram

Fault Protection mode is enabled by setting the Fault Protection Enable (FPEN1) bit and trig-

gered by a change in logic level at external interrupt pin (INT0). Alternatively, fault protection

mode can be triggered by the Analog Comparator Output (ACO).

When Fault Protection is triggered, the COM1x bits are cleared, Output Comparators are discon-

nected from the PWM output pins and PORTB register bits are connected to the PWM output

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

clk

PCK

clk

(clk

PCK /8)

TOVn

TCNTn

BOTTOM + 1

BOTTOM

BOTTOM + 1

clk

PCK

clk

(clk

PCK /8)

Analog

Comparator

Noise

Canceler

INT0

Edge

Detector

FPAC1

FPNC1

FPES1

ACO*

FPEN1

Timer/Counter1

FAULT_PROTECTION (Int. Req.)

ATtiny261A Datasheet(PDF) 105 Page - ATMEL Corporation

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