ATtiny261A datasheet(106/292 Pages) ATMEL

106 / 292 page

106

8197A–AVR–10/09

ATtiny261A/461A/861A

pins. The Fault Protection Enable (FPEN1) is automatically cleared at the same system clock as

the COM1nx bits are cleared.

If the Fault Protection Interrupt Enable bit (FPIE1) is set, a Fault Protection interrupt is generated

and the FPEN1 bit is cleared. Alternatively the FPEN1 bit can be polled by software to figure out

when the Timer/Counter has entered to Fault Protection mode.

12.10.1

Fault Protection Trigger Source

The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alterna-

tively the Analog Comparator output can be used as trigger source for the Fault Protection unit.

The Analog Comparator is selected as trigger source by setting the Fault Protection Analog

Comparator (FPAC1) bit in the Timer/Counter1 Control Register (TCCR1D). Be aware that

changing trigger source can trigger a Fault Protection mode. Therefore it is recommended to

clear the FPF1 flag after changing trigger source, setting edge detector or enabling the Fault

Protection.

Both the external interrupt pin (INT0) and the Analog Comparator output (ACO) inputs are sam-

pled using the same technique as with the T0 pin (see Figure 11-3 on page 72). The edge

detectors are also identical but when the noise canceler is enabled additional logic is activated

before the edge detector, increasing the propagation delay with four system clock cycles.

An Input Capture can also be triggered by software by controlling the port of the INT0 pin.

12.10.2

Noise Canceler

The noise canceler uses a simple digital filtering technique to improve noise immunity. Consecu-

tive samples are monitored in a pipeline four units deep. The signal going to the edge detecter is

allowed to change only when all four samples are equal.

The noise canceler is enabled by setting the Fault Protection Noise Canceler (FPNC1) bit in

Timer/Counter1 Control Register D (TCCR1D). When enabled, the noise canceler introduces an

additional delay of four system clock cycles to a change applied to the input.

The noise canceler uses the system clock directly and is therefore not affected by the prescaler.

12.11 Accessing 10-Bit Registers

If 10-bit values are written to the TCNT1 and OCR1A/B/C/D registers, the 10-bit registers can be

byte accessed by the AVR CPU via the 8-bit data bus using two read or write operations. The

10-bit registers have a common 2-bit Timer/Counter1 High Byte Register (TC1H) that is used for

temporary storing of the two MSBs of the 10-bit access. The same TC1H register is shared

between all 10-bit registers. Accessing the low byte triggers the 10-bit read or write operation.

When the low byte of a 10-bit register is written by the CPU, the high byte stored in the TC1H

When the low byte of a 10-bit register is read by the CPU, the high byte of the 10-bit register is

copied into the TC1H register in the same clock cycle as the low byte is read.

To do a 10-bit write, the high byte must be written to the TC1H register before the low byte is

written. For a 10-bit read, the low byte must be read before the high byte.

12.11.1

Reusing the temporary high byte register

If writing to more than one 10-bit register where the high byte is the same for all registers written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

ATtiny261A Datasheet(PDF) 106 Page - ATMEL Corporation

ATtiny261A Datasheet(HTML) 106 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL