ATtiny261A datasheet(114/292 Pages) ATMEL

114 / 292 page

114

8197A–AVR–10/09

ATtiny261A/461A/861A

The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the

Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can

be generated. The Dead Time prescaler is controlled by two bits DTPS11 and DTPS10 from the

Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler.

The division factors are given in Table 12-16.

• Bits 3 : 0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

The Stop condition provides a Timer Enable/Disable function.

Table 12-16. Division factors of the Dead Time prescaler

DTPS11

DTPS10

Prescaler divides the T/C1 clock by

1x (no division)

Table 12-17. Timer/Counter1 Prescaler Select

CS13

CS12

CS11

CS10

Asynchronous Clocking Mode

Synchronous Clocking Mode

0000

T/C1 stopped

0001

PCK

0010

PCK/2

CK/2

0011

PCK/4

CK/4

0100

PCK/8

CK/8

0101

PCK/16

CK/16

0110

PCK/32

CK/32

0111

PCK/64

CK/64

1000

PCK/128

CK/128

1001

PCK/256

CK/256

1010

PCK/512

CK/512

1011

PCK/1024

CK/1024

1100

PCK/2048

CK/2048

1101

PCK/4096

CK/4096

1110

PCK/8192

CK/8192

1111

PCK/16384

CK/16384

ATtiny261A Datasheet(PDF) 114 Page - ATMEL Corporation

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