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ATtiny261A Datasheet(PDF) 117 Page - ATMEL Corporation |
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ATtiny261A Datasheet(HTML) 117 Page - ATMEL Corporation |
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117 / 292 page  117 8197A–AVR–10/09 ATtiny261A/461A/861A • Bit 3 - FPAC1: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Fault Protection interrupt. When written logic zero, no con- nection between the Analog Comparator and the Fault Protection function exists. To make the comparator trigger the Timer/Counter1 Fault Protection interrupt, the FPIE1 bit in the Timer/Counter1 Control Register D (TCCR1D) must be set. • Bit 2- FPF1: Fault Protection Interrupt Flag When the FPIE1 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will cause an interrupt request even, if the Fault Protection pin is configured as an output. The corre- sponding interrupt of Fault Protection Interrupt Request is executed from the Fault Protection Interrupt Vector. The bit FPF1 is cleared by hardware when executing the corresponding inter- rupt handling vector. Alternatively, FPF1 is cleared after a synchronization clock cycle by writing a logical one to the flag. When the SREG I-bit, FPIE1 and FPF1 are set, the Fault Interrupt is executed. • Bits 1:0 - WGM11, WGM10: Waveform Generation Mode Bits These bits together with the PWM1A/PWM1B bits control the counting sequence of the counter and the type of waveform generation to be used, as shown in Table 12-21. Modes of operation supported by the Timer/Counter1 are: Normal mode (counter), Fast PWM Mode, Phase and Fre- quency Correct PWM and PWM6 Modes. 12.12.5 TCCR1E – Timer/Counter1 Control Register E • Bits 7:6 - Res: Reserved Bits These bits are reserved and always read zero. • Bits 5:0 – OC1OE5:OC1OE0: Output Compare Override Enable Bits These bits are the Ouput Compare Override Enable bits that are used to connect or disconnect the Output Compare Pins in PWM6 Modes with an instant response on the corresponding Out- put Compare Pins. The actual value from the port register will be visible on the port pin, when Table 12-21. Waveform Generation Mode Bit Description PWM1A/ PWM1B WGM11:10 Timer/Counter Mode of Operation TOP Update OCR1x at Set TOV1 Flag at 0 XX Normal OCR1C Immediate TOP 1 00 Fast PWM OCR1C TOP TOP 1 01 Phase & Frequency Correct PWM OCR1C BOTTOM BOTTOM 1 10 PWM6 / Single-slope OCR1C TOP TOP 1 11 PWM6 / Dual-slope OCR1C BOTTOM BOTTOM Bit 76543210 0x00 (0x20) - - OC1OE5 OC1OE4 OC1OE3 OC1OE2 OC1OE1 OC1OE0 TCCR1E Read/Write R R R/W R/W R/W R/W R/W R/W Initial value 00000000 |
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