ATtiny261A datasheet(121/292 Pages) ATMEL

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121

8197A–AVR–10/09

ATtiny261A/461A/861A

Note that, if 10-bit accuracy is used special procedures must be followed when accessing the

internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are

described in section “Accessing 10-Bit Registers” on page 106.

12.12.13 TIMSK – Timer/Counter1 Interrupt Mask Register

• Bit 7- OCIE1D: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1D bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchD, interrupt is enabled. The corresponding interrupt at vector

$010 is executed if a compare matchD occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector

$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector

$009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR.

12.12.14 TIFR – Timer/Counter1 Interrupt Flag Register

• Bit 7- OCF1D: Output Compare Flag 1D

The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1D is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1D, and OCF1D

are set (one), the Timer/Counter1 D compare match interrupt is executed.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing

Bit

76543210

0x39 (0x59)

OCIE1D

OCIE1A

OCIE1B

OCIE0A

OCIE0B

TOIE1

TOIE0

TICIE0

TIMSK

Read/Write

R/W

Initial value

00000000

Bit

76543210

0x38 (0x58)

OCF1D

OCF1A

OCF1B

OCF0A

OCF0B

TOV1

TOV0

ICF0

TIFR

Read/Write

R/W

Initial value

00000000

ATtiny261A Datasheet(PDF) 121 Page - ATMEL Corporation

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