ATtiny261A datasheet(122/292 Pages) ATMEL

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8197A–AVR–10/09

ATtiny261A/461A/861A

the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A

are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B

are set (one), the Timer/Counter1 B compare match interrupt is executed.

• Bit 2 - TOV1: Timer/Counter1 Overflow Flag

In Normal Mode and Fast PWM Mode the TOV1 bit is set (one) each time the counter reaches

TOP at the same clock cycle when the counter is reset to BOTTOM. In Phase and Frequency

Correct PWM Mode the TOV1 bit is set (one) each time the counter reaches BOTTOM at the

same clock cycle when zero is clocked to the counter.

The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vec-

tor. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to

the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and

TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.

12.12.15 DT1 – Timer/Counter1 Dead Time Value

The dead time value register is an 8-bit read/write register.

The dead time delay of all Timer/Counter1 channels are adjusted by the dead time value regis-

ter, DT1. The register consists of two fields, DT1H3:0 and DT1L3:0, one for each

complementary output. Therefore a different dead time delay can be adjusted for the rising edge

of OC1x and the rising edge of OC1x.

• Bits 7:4- DT1H3:DT1H0: Dead Time Value for OC1x Output

The dead time value for the OC1x output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

• Bits 3:0- DT1L3:DT1L0: Dead Time Value for OC1x Output

The dead time value for the OC1x output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

Bit

76543210

0x24 (0x44)

DT1H3

DT1H2

DT1H1

DT1H0

DT1L3

DT1L2

DT1L1

DT1L0

DT1

Read/Write

R/W

Initial value

00000000

ATtiny261A Datasheet(PDF) 122 Page - ATMEL Corporation

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