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ATtiny261A Datasheet(PDF) 154 Page - ATMEL Corporation |
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ATtiny261A Datasheet(HTML) 154 Page - ATMEL Corporation |
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154 / 292 page  154 8197A–AVR–10/09 ATtiny261A/461A/861A 15.13.2 ADCL and ADCH – The ADC Data Register 15.13.2.1 ADLAR = 0 15.13.2.2 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 151. 15.13.3 ADMUX – ADC Multiplexer Selection Register 10 0 16 10 1 32 11 0 64 1 1 1 128 Table 15-3. ADC Prescaler Selections (Continued) ADPS2 ADPS1 ADPS0 Division Factor Bit 15 14 13121110 9 8 0x05 (0x25) –––––– ADC9 ADC8 ADCH 0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 76543210 Read/Write RRRRR RRR RRRRR RRR Initial Value 00000000 00000000 Bit 15 14 13121110 9 8 0x05 (0x25) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH 0x04 (0x24) ADC1 ADC0 –––––– ADCL 76543210 Read/Write RRRRR RRR RRRRR RRR Initial Value 00000000 00000000 Bit 7 6 543210 0x07 (0x27) REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 000000 |
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