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LPC1313 Datasheet(PDF) 18 Page - NXP Semiconductors

Part # LPC1313
Description  32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and 8 kB SRAM; USB device
PDF  53 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC1313 Datasheet(HTML) 18 Page - NXP Semiconductors

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LPC1311_13_42_43_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 11 December 2009
18 of 53
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
7.9 USB interface (LPC1342/43 only)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1342/43 USB interface is a device controller with on-chip PHY for device
functions.
7.9.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
7.9.1.1
Features
• Fully compliant with USB 2.0 specification (full speed).
• Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per
endpoint (see Table 5).
• Supports Control, Bulk, Isochronous, and Interrupt endpoints.
• Supports SoftConnect feature.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.10 UART
The LPC1311/13/42/43 contains one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
Table 5.
USB device endpoint configuration
Logical
endpoint
Physical
endpoint
Endpoint type
Direction
Packet size
(byte)
Double buffer
0
0
Control
out
64
no
0
1
Control
in
64
no
1
2
Interrupt/Bulk
out
64
no
1
3
Interrupt/Bulk
in
64
no
2
4
Interrupt/Bulk
out
64
no
2
5
Interrupt/Bulk
in
64
no
3
6
Interrupt/Bulk
out
64
yes
3
7
Interrupt/Bulk
in
64
yes
4
8
Isochronous
out
512
yes
4
9
Isochronous
in
512
yes



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