LPC1313 datasheet(23/53 Pages) NXP

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LPC1311_13_42_43_1

Product data sheet

Rev. 01 — 11 December 2009

23 of 53

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

Upon power-up, any chip reset, or wake-up from Deep power-down mode, the

LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of

the other available clock sources.

7.17.1.2

System oscillator

The system oscillator can be used as the clock source for the CPU, with or without using

the PLL. On the LPC134x, the system oscillator must be used to provide the clock source

to USB.

The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be

boosted to a higher frequency, up to the maximum CPU operating frequency, by the

system PLL.

7.17.2 System PLL and USB PLL

The LPC134x contain a system PLL and a dedicated PLL for generating the 48 MHz USB

clock. The LPC131x contain the system PLL only. The system and USB PLLs are

identical.

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).

The multiplier can be an integer value from 1 to 32. The CCO operates in the range of

156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within

its frequency range while the PLL is providing the desired output frequency. The output

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must conﬁgure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is 100

µs.

7.17.3 Clock output

The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the

system oscillator, the watchdog oscillator, or the main clock to an output pin.

7.17.4 Wake-up process

The LPC1311/13/42/43 begin operation at power-up and when awakened from Deep

power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows

chip operation to resume quickly. If the main oscillator or the PLL is needed by the

application, software will need to enable these features and wait for them to stabilize

before they are used as a clock source.

7.17.5 Power control

The LPC1311/13/42/43 support a variety of power control features. There are three

special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep

power-down mode. The CPU clock rate may also be controlled as needed by changing

clock sources, reconﬁguring PLL values, and/or altering the CPU clock divider value. This

allows a trade-off of power versus processing speed based on application requirements.

In addition, a register is provided for shutting down the clocks to individual on-chip

peripherals, allowing ﬁne tuning of power consumption by eliminating all dynamic power

use in any peripherals that are not required for the application. Selected peripherals have

their own clock divider which provides even better power control.

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