LPC1313 datasheet(15/53 Pages) NXP

15 / 53 page

LPC1311_13_42_43_1

Product data sheet

Rev. 01 — 11 December 2009

15 of 53

NXP Semiconductors

LPC1311/13/42/43

32-bit ARM Cortex-M3 microcontroller

interruptible/continuable multiple load and store instructions, automatic state save and

restore for interrupts, tightly integrated interrupt controller, and multiple core buses

capable of simultaneous accesses.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM Cortex-M3 processor is described in detail in the

Cortex-M3 Technical

Reference Manual which is available on the ofﬁcial ARM website.

7.3 On-chip ﬂash program memory

The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or

8 kB (LPC1311) of on-chip ﬂash memory.

7.4 On-chip SRAM

The LPC1311/13/42/43 contain a total of 8 kB (LPC1343 and LPC1313) or 4 kB

(LPC1342 and LPC1311) on-chip static RAM memory.

7.5 Memory map

The LPC134x incorporates several distinct memory regions, shown in the following

ﬁgures. Figure 6 shows the overall map of the entire address space from the user program

viewpoint following reset. The interrupt vector area supports address remapping.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.

The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.

Each peripheral of either type is allocated 16 kB of space. This allows simplifying the

address decoding for each peripheral.

LPC1313 Datasheet(PDF) 15 Page - NXP Semiconductors