AS3525 datasheet(123/194 Pages) AMSCO

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AS3525-A/-B C22O22

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.13

123

- 194

7.4.3

Low Drop Out Regulators

7.4.3.1

General

These LDO’s are designed to supply sensitive analogue circuits, audio devices, AD and DA converters, micro-controller and other peripheral

devices.

The design is optimised to deliver the best compromise between quiescent current and regulator performance for battery powered devices.

Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U). The low ESR of these caps ensures low

output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to

operate in linear mode. Power supply rejection is high enough to suppress high ripple on the battery at the output. The low noise performance

allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power device enables the device

to deliver up to 150mA even at nearly discharged batteries without any decrease of performance.

Figure 47 LDO Block Diagram

7.4.3.2

LDO1

This LDO generates the analog supply voltage used for the AFE itself.

•

Input voltage is BVDD

•

Output voltage is AVDD (typ. 2.9V)

7.4.3.3

LDO2

This LDO generates the digital supply voltage used for the AFE itself.

•

Input Voltage is BVDD

•

Output Voltage is DVDD (typ. 2.9V)

•

Driver strength: 200mA

7.4.3.4

LDO3

This LDO can used to generate the periphery voltage for the digital processor (e.g. vdd_mem for MPMC interface)

•

Input Voltage BVDD

•

Output Voltage is PVDD 1.7 to 3.3V

•

Driver strength: 200mA

•

Programmable via P_PVDD pin and PVDDp bit in 8 steps

Table 101 PVDD programming

P_PVDD

PVDDp=0

PVDDp=1

VSS

OFF

150k to VSS

2.50V

2.36V

Open

3.33V

3.15V

150k to DVDD

2.90V

2.74V

DVDD

1.80V

1.70V

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