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S5LS20216BSPGETQ1R Datasheet(PDF) 49 Page - Texas Instruments |
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S5LS20216BSPGETQ1R Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 101 page  ETM DMM TAP RTP TAP TDI TDO DAP TPIU debug scan chain #0 debug scan chain #1 CPU POM DMM RTP boundary scan interface 0 1 CoreSight Boundary Scan TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141 – MARCH 2010 4.7 ETM The device contains an ARM Cortex™-R4F External Trace Macrocell (ETM-R4) with a 32bit data port. The ETM-R4 module is connected to a Test Port Interface Unit (TPIU) with a 32bit data bus. The ETM-R4 is CoreSight compliant and follows the ARM ETM v3 specification; for more details see ARM CoreSight™ ETM-R4 TRM specification Revr0p0. The ETM-R4 supports "half rate clocking" only. The ETM clock source can be selected as either VCLK or the external ETMTRACECLKIN pin. The selection is done by the EXTCTRLOUT[1:0] control bits of the TPIU; the default is '00'. Table 4-12. ETMTRACECLKIN Selection EXTCTRLOUT[1:0] TPIU/TRACECLKIN 0 tied-low 1 VCLK 10 ETMTRACECLKIN 11 tied-zero 4.8 Debug Scan Chains The device contains an ICEPICK module to access the debug scan chains. Debug scan chain #0 handles the access to the CPU, to the ETM-R4 (External Trace Macrocell), to the POM (Parameter Overlay Module) and to the TPIU (Test Port Interface Unit). Debug scan chain #1 handles the access to the Ram Trace Port (RTP) and the Data Modification Module (DMM) which each incorporate a dedicated TAP (Test Access Port) controller. Each module is selected via its scan chain number. The IcePick scan ID is 0x80206D05, which is the same number as the device ID. Figure 4-1. Debug Scan Chains Copyright © 2010, Texas Instruments Incorporated Peripherals 49 Submit Documentation Feedback Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 |
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