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S5LS20216BSPGETQ1R Datasheet(PDF) 59 Page - Texas Instruments |
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S5LS20216BSPGETQ1R Datasheet(HTML) 59 Page - Texas Instruments |
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59 / 101 page  TMS570LS20216, TMS570LS20206, TMS570LS10216 TMS570LS10206, TMS570LS10116, TMS570LS10106 www.ti.com SPNS141 – MARCH 2010 5.3 PLL Registers The default values for the PLL (Phase Locked Loop) control registers are shown in this section. PLLCTL1 and PLLCTL2 are used to configure PLL1 (F035 FMzPLL) and PLLCTL3 is used to configure PLL2 (F035 FPLL). Figure 5-4. PLLCTL1 Register (Location: 0xFFFF FF70) 31 30 29 28 27 26 25 23 223 21 20 19 18 17 16 ROS BPOS[1:0] PLLDIV[4:0] ROF RESERVED REFCLKDIV[5:0] R/WP- R/WP-01 R/WP-111 R/WP- R-0 R/WP-000010 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLLMUL[15:0] R/WP-01011111000000000101 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device specific Figure 5-5. PLLCTL2 Register (Location: 0xFFFF FF74) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FMEN SPREADINGRATE[8:0] RESV EWADJ[8:4] A R/WP- R/WP-111111111 R-0 R/WP-00000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BWADJ[3:0] ODPLL SPR_AMOUNT[8:0] R/WP-0111 R/WP-001 R/WP-000000000 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D = device specific NOTE There are several combinations of the modulation depth and modulation frequency that are not allowed. Valid settings for this device include the following: TBD Figure 5-6. PLLCTL3 Register (Location: 0xFFFF E100) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESERVED OSC RESERVED DIV R/W-000000000 R/WP- R/W-000000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED PLL_MUL[3:0] RESERVED PLL_DIV [2:0] R/W-000000 R/WP-011 R/W-00000 R/WP 111 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; D= device specific Copyright © 2010, Texas Instruments Incorporated Device Registers 59 Submit Documentation Feedback Product Folder Link(s): TMS570LS20216 TMS570LS20206 TMS570LS10216 TMS570LS10206 TMS570LS10116 TMS570LS10106 |
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