MPC5200B_10 datasheet(26/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

NOTES:

1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from

0–65535.

2. Example:

Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst

on the internal XLB is executed. => LB = 1

Data bus width is 8 bit. => DS = 8

=> 41 ×2×(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.

Wait State is set to 10. => WS = 10

1+ 10 + 32 = 43 => CS is asserted for 43 PCI cycles.

3. ACK is output and indicates the burst.

4. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration

happens the bus can be driven within 4 IPB clocks by an other modules.

Figure 12. Timing Diagram—Burst Mode

DATA hold after rising edge of PCI

clock

—ns

—

A7.32

t10

DATA hold after CS negation

(DC + 1) × tPCIck

(4)

A7.33

t11

ACK assertion after CS assertion

—(WS + 1) × tPCIck

—

A7.34

t12

ACK negation before CS negation

—7.0

(3)

A7.35

t13

ACK pulse width

4LB ×2×(32/DS) ×tPCIck 4

LB ×2×(32/DS)×t

PCIck

(2),(3)

A7.36

t14

CS assertion after TS assertion

—2.5

—

A7.37

t15

TS pulse width

tPCIck

—

A7.38

Table 25. Burst Mode Timing (continued)

Sym

Description

Min

Max

Units Notes SpecID

ADDR

DATA (rd)

CS[x]

R/W

t10

ACK

PCI CLK

t11

t13

t14

t15

t12

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