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MPC5200B Datasheet(PDF) 15 Page - Freescale Semiconductor, Inc |
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MPC5200B Datasheet(HTML) 15 Page - Freescale Semiconductor, Inc |
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15 / 72 page  MPC5200B Data Sheet, Rev. 4 Freescale Semiconductor 15 For additional information, see the MPC5200B User’s Manual (MPC5200BUM). 1.3.4.1 Reset Configuration Word During reset (HRESET and PORRESET) the Reset Configuration Word is latched in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and PORRESET) are inactive (high), the contents of this register are locked immediately with the SYS_XTAL clock (see Figure 3). Figure 3. Reset Configuration Word Locking NOTE Beware of changing the values on the pins of the reset configuration word after the deassertion of PORRESET. This may cause problems because it may change the internal clock ratios and so extend the PLL locking process. 1.3.5 External Interrupts The MPC5200B provides three different kinds of external interrupts: • Four IRQ interrupts • Eight GPIO interrupts with simple interrupt capability (not available in power-down mode) • Eight WakeUp interrupts (special GPIO pins) The propagation of these three kinds of interrupts to the core is shown in the following graphic: sample sample sample sample sample sample sample sample sample sample LOCK RST_CFG_WRD HRESET PORRESET SYS_XTAL 4096 clocks |
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