WM8170 datasheet(14/41 Pages) WOLFSON

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WM8170

Product Preview Rev 1.0

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 March 2000

DEVICE DESCRIPTION

GENERAL OPERATION

The analogue circuitry within the WM8170 consists of a Sample/Hold (S/H) block, a Programmable

Gain Amplifier (PGA), a DC Offset Correction loop, and a 10-bit 21MSPS Analogue to Digital

Converter (ADC). The Sample/Hold block takes a Correlated Double Sample (CDS) of the incoming

video. The CDS video sample is transferred differentially into the PGA block, which is used to gain

the signal to the full dynamic range of the ADC. The PGA is controlled digitally via the management

interface. The 10-bit pipeline ADC takes the output from the PGA and converts the analogue voltage

into a digital representation of the signal.

To correct for DC offsets in the input video, the Sample/Hold block and the PGA, DC offset correction

circuitry is provided under the control of external inputs. An analogue correction loop using mixed

mode circuitry removes the majority of the DC offset by summing the output of a DAC into the main

signal path. An up/down counter controlled from the output of a comparator updates the DAC. The

comparator checks the output from the PGA against a voltage representing the target black level. As

the analogue correction loop does not correct for DC offsets in either the ADC or the comparator in

the feedback loop, a further digital offset is automatically calculated within the digital section following

the ADC, which forces the digital output to the previously programmed value.

Two auxiliary 8-bit DACs are provided, which can be used within the camera system to control bias

voltages to the area CCD, or to provide DC voltages for peripheral camera functions, such as auto-

focus control.

To allow the registers within the WM8170 to be programmed a management interface is provided

which allows either serial or parallel control. The interface allows the user to both write to, and read

from the internal registers, which eases system debug as values previously programmed can

be checked.

INPUT SAMPLE AND HOLD, AND VIDEO TIMING

The WM8170 includes a Sample/Hold section at its input, which is used to acquire samples from the

analogue output of the area array CCD. The Sample/Hold is configured as shown in Figure 9, and

can be operated in a basic Sample and Hold mode or in Correlated Double Sampling (CDS) mode.

In CDS, the input video reset level is sampled under the control of the signal applied to the SHP

digital input and the input video signal level is sampled under the control of the signal applied to the

SHD digital input.

The Sample/Hold produces a differential voltage output signal, which is passed to the following PGA.

Detailed input timing of the Sample/Hold is shown in Figures 10 and 11. Note that there should be no

overlap between the SHP and SHD pulses. Any overlap will cause the WM8170 to operate

incorrectly. The WM8170 can be programmed via the management interface to accept SHP and SHD

inputs as either both positive, or both negative pulses. Control of this function is via the control bit

INVSHX.

WM8170 Datasheet(PDF) 14 Page - Wolfson Microelectronics plc