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SS4035G

1/09/2006 Rev.3.01

If

any cell voltage is greater than the other by 0.02V

transistor and sends a small current through resistor

or more, the corresponding balance control output

Rb. This slows down charging of the corresponding cell.

goes high. It then turns on the corresponding by-pass

The balance circuit turns off when the cells are balanced.

CHARGING CONTROL

AVDD

16

CCTL

5

VDD

13

TESTIN

3

CLED

1

TESTOUT

4

CFLED

2

V2

12

S3

15

BA2

18

S2

20

V1

11

S1

19

BA1

17

RES

7

FC

6

ROSC

14

T

9

GND

8

I

10

U?

SS4035G

1k

Ω

3.3k

Ω

10k

Ω

NPN

CAP

V+

VB+

VDD

Figure 5 shows the linear charger mode for the

MOSFET which is operating in the active region.

SS4035G. The output of pin CCTL (5) is a pulse-

This P-channel MOSFET must be chosen carefully

width modulated (PWM) signal. This signal is

to handle the required power dissipation.

translated to a DC voltage to control the P-channel

DIGITAL CONTROLS

AVDD

16

CCTL

VDD

13

TESTIN

CLED

1

TESTOUT

CFLED

2

V2

S3

15

BA2

S2

20

V1

S1

19

BA1

RES

7

FC

ROSC

14

T

GND

8

I

SS4035G

3K

3K

47K 8.6K

LED

LED

1nF

VDD

Figure 6 shows the connections for the digital pins

have internal pull-ups. Table 1 shows the options

for the SS4035G. Selection pins S1, S2 and S3

for selecting the required voltage for Isense.

Figure 5. Charging Control

Figure 6. Current Selection and Logic Control

P-channel

MOSFET