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74LVC1G99GD Datasheet(PDF) 17 Page - NXP Semiconductors |
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74LVC1G99GD Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 29 page ![]() 74LVC1G99_4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 16 April 2010 17 of 29 NXP Semiconductors 74LVC1G99 Ultra-configurable multiple function gate; 3-state 12. Waveforms Measurement points are given in Table 25. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 21. The data input (A, B, C, D) to output (Y) propagation delays 001aah341 tPLH tPHL tPHL VM VM VM VM VM VI GND A, B, C, D input Y output Y output VOH VOL VOH VOL VM tPLH Measurement points are given in Table 25. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 22. 3-state enable and disable times mna644 tPLZ tPHZ outputs disabled outputs enabled VY VX outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH OE input VI VOL VOH VCC VM GND GND tPZL tPZH VM VM Table 25. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH − 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V |
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