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74LVC3G17GD Datasheet(PDF) 3 Page - NXP Semiconductors |
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74LVC3G17GD Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 18 page ![]() 74LVC3G17_6 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 — 6 June 2008 3 of 18 NXP Semiconductors 74LVC3G17 Triple non-inverting Schmitt trigger with 5 V tolerant input 7. Pinning information 7.1 Pinning Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT833-1 (XSON8) 74LVC3G17 1A VCC 3Y 1Y 2A 3A GND 2Y 001aab106 1 2 3 4 6 5 8 7 74LVC3G17 3A 1Y VCC 2Y 2A 3Y 1A GND 001aac023 36 27 18 45 Transparent top view Fig 6. Pin configuration SOT996-2 (XSON8U) Fig 7. Pin configuration SOT902-1 (XQFN8U) 001aai246 74LVC3G17 Transparent top view 8 7 6 5 1 2 3 4 1A 3Y 2A GND VCC 1Y 3A 2Y 001aag404 3Y 3A 1A 2A 1Y 2Y Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC3G17 |
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