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09HSI-S042-R0-CHT Datasheet(PDF) 49 Page - Hirose Electric |
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09HSI-S042-R0-CHT Datasheet(HTML) 49 Page - Hirose Electric |
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49 / 71 page ![]() Signal Integrity Report – IT3 (17mm) Page 49 transitions. All PCB traces coming out from the vias have been matched to 10.507mm. The results at various frequencies of interest are summarized in Table 22. Figure 79 and Figure 80 show the power sum of NEXT and FEXT for the cascaded model (vias + connector + vias) of the single-ended center port. Figure 78 S-parameters for port 15 of cascaded vias+connector+vias transition with routing on layer 16 FREQUENCY (GHZ) INSERTION LOSS (DB) RETURN LOSS (DB) WORST PAIR-TO-PAIR NEXT (DB) WORST PAIR-TO-PAIR FEXT (DB) 400 -0.178 -38.10 -28.35 -33.14 533 -0.228 -36.82 -26.51 -30.95 800 -0.323 -35.14 -24.76 -27.95 Table 22 Summary of S-parameters for port 15 of cascaded vias+connector+vias transition with routing on layer 16 Figure 79 Power Sum of NEXT for port 15 of vias+connector+vias transition with routing on layer 16 |
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