09HSI-S042-R0-CHT datasheet(28/71 Pages) HIROSE

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Signal Integrity Report – IT3 (17mm)

Page 28

Figure 46 Impedance profile for top corner pair 15 of IT3-17mm (connector only) @60ps rise time (20% to 80%) and 5.25GHz

BW, and @30ps rise time (20% to 80%) and 10.5GHz BW

The receptacles show higher impedance in the connector-only TDR waveforms because IT3 was

designed intentionally with slightly higher impedance in the receptacle to offset the via’s (and via

stub’s) low impedance, as shown in the next section.

3.2.2 Impedance Profile (vias + connector + vias)

The impedance profiles for center pair 8, right edge pair 10, top edge pair 14, and top corner

pair 15 of the fully populated model (vias + connector + vias), as portrayed in Figure 42, are shown

in Figure 47, Figure 48, Figure 49 and Figure 50. The via models for center pair 8 and right edge

pair 10 are routed on layer 16, the top edge pair 14 vias are routed on layer 28 (short via stub), and

the vias for the top corner pair 15 are routed on layer 19.

Figure 47 Impedance profile for center pair 8 of IT3-17mm (vias+connector+vias) with routing on layer 16 @60ps rise time (20%

to 80%) and 5.25GHz BW, and @30ps rise time (20% to 80%) and 10.5GHz BW

Vias Interposer

Vias

Receptacle Receptacle

09HSI-S042-R0-CHT Datasheet(PDF) 28 Page - Hirose Electric