09HSI-S042-R0-CHT datasheet(36/71 Pages) HIROSE

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Signal Integrity Report – IT3 (17mm)

Page 36

3.2.4.2 60% density pin assignment

Figure 61 Differential cross-talk (in %) from simulations for pair 4 of 60% pin density configuration and step input @ 60ps (20%

to 80%) rise time and 5.25GHz BW

3.2.4.3 50% density pin assignment

Figure 62 Differential cross-talk (in %) from simulations for pair 4 of 50% pin density configuration and step input @ 60ps (20%

to 80%) rise time and 5.25GHz BW

3.2.5 System Voltage and Timing Margins

To demonstrate the IT3’s performance, we ran simulations for the following setup:

Ideal voltage source with package via.

Center pair of the IT3 connector with via transition in the 16th PCB routing layer.

152.4mm (6 inches) PCB trace from driver to IT3 connector, and 152.4mm (6 inches)

PCB trace from IT3 connector to receiver, including via transition to the receiver.

The 16th routing layer was chosen to demonstrate that the channel works even with long via

stubs of ~60mil, which allows for more design flexibility.

Note: Since the time steps used for the simulations were of 1ps, the timing jitter values have an

error margin of 1ps. The eye height is defined as the absolute maximum eye opening.

3.2.5.1 Fully populated pin assignment

The full channel includes package-via models without crosstalk effects at the transmitter and

receiver. The following eye diagrams account for these package-via effects, which are not included

in the channel model defined in the IEEE 802.3ap spec. For the center-pair channel, the models for

package via and connector via are identical (i.e. same via stub length).

Table 10, Table 11 and Table 12 show the optimized tap coefficients for the maximum eye

opening at various data rates for the channel without the connector and connector vias (Base Case

1), for the channel without the connector only (Base Case 2), and for the full channel.

09HSI-S042-R0-CHT Datasheet(PDF) 36 Page - Hirose Electric