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TMS320DM368ZCEF Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM368ZCEF Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 208 page  TMS320DM368 www.ti.com SPRS668A – APRIL 2010 TMS320DM368 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM368 1 TMS320DM368 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 • Highlights • ARM926EJ-S™ Core – High-Performance Digital Media – Support for 32-Bit and 16-Bit System-on-Chip (DMSoC) (Thumb® Mode) Instruction Sets – 432-MHz ARM926EJ-S Clock Rate – DSP Instruction Extensions and Single Cycle MAC – Two Video Image Co-processors (HDVICP, MJCP) Engines – ARM® Javelle® Technology – Supports a Range of Encode, Decode, and – Embedded ICE-RT Logic for Real-Time Video Quality Operations Debug – Video Processing Subsystem • ARM9 Memory Architecture • HW Face Detect Engine – 16K-Byte Instruction Cache • Resize Engine from 1/16x to 8x – 8K-Byte Data Cache • 16-Bit Parallel AFE (Analog Front-End) – 32K-Byte RAM Interface Up to 120 MHz – 16K-Byte ROM • 4:2:2 (8-/16-bit) Interface – Little Endian • 3 DACs for HD Analog Video Output • Two Video Image Co-processors • Hardware On-Screen Display (OSD) (HDVICP, MJCP) Engines – Capable of 1080p 30fps H.264 video – Support a Range of Encode and Decode processing Operations – Peripherals include EMAC, USB 2.0 OTG, – H.264, MPEG4, MPEG2, MJPEG, JPEG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 WMV9/VC1 MMC/SD/SDIO, Key Scan • Video Processing Subsystem – 8 Different Boot Modes and Configurable – Front End Provides: Power-Saving Modes • HW Face Detect Engine – Pin-to-pin and software compatible with • Hardware IPIPE for Real-Time Image DM365 Processing – Extended temperature (-40ºC – 85ºC) – Resize Engine available – Resize Images From 1/16x to 8x – 3.3-V and 1.8-V I/O, 1.35-V Core – Separate Horizontal/Vertical – Debug Interface Support Control – 338-Pin Ball Grid Array at 65nm Process – Two Simultaneous Output Paths Technology • IPIPE Interface (IPIPEIF) • High-Performance Digital Media • Image Sensor Interface (ISIF) and CMOS System-on-Chip (DMSoC) Imager Interface – 432-MHz ARM926EJ-S Clock Rate • 16-Bit Parallel AFE (Analog Front End) – 4:2:2 (8-/16-Bit) Interface Interface Up to 120 MHz – Capable of 1080p 30fps H.264 video • Glueless Interface to Common Video processing Decoders – Pin compatible with DM365 processors • BT.601/BT.656/BT.1120 Digital YCbCr – Fully Software-Compatible With ARM9™ 4:2:2 (8-/16-Bit) Interface – Extended temperature available for 432-Mhz • Histogram Module device 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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