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TMS320DM368ZCEF Datasheet(PDF) 22 Page - Texas Instruments |
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TMS320DM368ZCEF Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 208 page  TMS320DM368 SPRS668A – APRIL 2010 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State CIN1(5) A18 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[1] YCC 16-bit: time multiplexed between chroma: CB/CR[01] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[01] CIN0(5) B17 I/O ISIF VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[0] YCC 16-bit: time multiplexed between chroma: CB/CR[00] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[00] YIN7(5) / GIO103 C12 I/O ISIF/ VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[15] /SPI3_SCLK GIO / SPI3 YCC 16-bit: time multiplexed between luma: Y[07] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[07] GIO: GIO[103] SPI3: Clock YIN6(5) / GIO102 A13 I/O ISIF / VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[14] /SPI3_SIMO GIO / SPI3 YCC 16-bit: time multiplexed between luma: Y[06] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[06] GIO: GIO[102] SPI3: Slave Input Master Output Data Signal YIN5(6) / GIO101 B13 I/O ISIF / VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[13] /SPI3_SCS[0] GIO / SPI3 YCC 16-bit: time multiplexed between luma: Y[05] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[05] GIO: GIO[101] SPI3: Chip Select 0 YIN4(6) / GIO100 / D12 I/O ISIF / VDD_ISIF18_33 IPD Input Standard ISIF Analog Front End (AFE): raw[12] SPI3_SOMI / GIO / SPI3_SCS[1] SPI3 YCC 16-bit: time multiplexed between luma: Y[04] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[04] GIO: GIO[100] SPI3: Slave Output Master Input Data Signal SPI3: Chip Select 1 (6) The Y input (YIN[7:0]) and C input (CIN[7:0]) buses can be swapped by programming the field bit YCINSWP in the VPFE CCD Configuration (CCDCFG) register (0x01C7 0136h). IF YCINSWP bit is 0 (default) YIN[7:0] = Y signal / CIN[7:0] = C signal . IF YCINSWP bit is 1 YIN[7:0] = C signal / CIN[7:0] = Y signal For more information, see the TMS320DM36x Video Processing Front End (VPFE) Reference Guide (literature number SPRUFG8). 22 Device Overview Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
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