HT48R02N datasheet(50/71 Pages) HOLTEK

50 / 71 page

HT46R01B/02B/01N/02N

HT48R01B/02B/01N/02N

Rev.1.10

February 12, 2010

When an interrupt request is generated it takes 2 or 3 in-

struction cycle before the program jumps to the interrupt

vector. If the device is in the Sleep Mode and is woken

up by an interrupt request then it will take 3 cycles be-

fore the program jumps to the interrupt vector.

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

· HT46R01B/HT46R02B/HT46R01N/HT46R02N

Interrupt Source

Priority Vector

External Interrupt

04H

Timer/Event Counter 0 Overflow

08H

Timer/Event Counter 1 Overflow

0CH

A/D Conversion Complete

10H

Time Base Overflow

14H

· HT48R01B/HT48R02B/HT48R01N/HT48R02N

Interrupt Source

Priority Vector

External Interrupt

04H

Timer/Event Counter 0 Overflow

08H

Timer/Event Counter 1 Overflow

0CH

Time Base Overflow

14H

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the interrupt

registers can prevent simultaneous occurrences.

External Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EMI, and external interrupt enable bit, INTE,

must first be set. An actual external interrupt will take

place when the external interrupt request flag, INTF, is

set, a situation that will occur when an edge transition

appears on the external INT line. The type of transition

that will trigger an external interrupt, whether high to low,

low to high or both is determined by the INTEG0 and

INTEG1 bits, which are bits 6 and 7 respectively, in the

CTRL1 control register. These two bits can also disable

the external interrupt function.

INTEG1

INTEG0

Edge Trigger Type

External interrupt disable

Rising edge Trigger

Falling edge Trigger

Both edge Trigger

The external interrupt pin is pin-shared with the I/O pin

PA3 and can only be configured as an external interrupt

pin if the corresponding external interrupt enable bit in

the INTC0 register has been set and the edge trigger

type has been selected using the CTRL1 register. The

pin must also be setup as an input by setting the corre-

sponding PAC.3 bit in the port control register. When the

interrupt is enabled, the stack is not full and a transition

appears on the external interrupt pin, a subroutine call to

the external interrupt vector at location 04H, will take

place. When the interrupt is serviced, the external inter-

rupt request flag, INTF, will be automatically reset and

the EMI bit will be automatically cleared to disable other

interrupts. Note that any pull-high resistor connections

on this pin will remain valid even if the pin is used as an

external interrupt input.

Wait for 2 ~ 3 Instruction Cycles

Main

Program

ISR Entry

Enable Bit Set ?

Main

Program

RETI

(it will set EMI automatically)

Automatically Disable Interrupt

Clear EMI & Request Flag

Interrupt Request or

Interrupt Flag Set by Instruction

Interrupt Flow

HT48R02N Datasheet(PDF) 50 Page - Holtek Semiconductor Inc

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