HT48R02N datasheet(36/71 Pages) HOLTEK

36 / 71 page

HT46R01B/02B/01N/02N

HT48R01B/02B/01N/02N

Rev.1.10

February 12, 2010

Timer Control Registers

- TMR0C, TMR1C

The flexible features of the Holtek microcontroller

Timer/Event Counters enable them to operate in three

different modes, the options of which are determined by

the contents of their respective control register.

The Timer Control Register is known as TMRnC. It is the

Timer Control Register together with its corresponding

timer register that control the full operation of the

Timer/Event Counter. Before the timer can be used, it is

essential that the Timer Control Register is fully pro-

grammed with the right data to ensure its correct opera-

tion, a process that is normally carried out during

program initialisation.

To choose which of the three modes the timer is to oper-

ate in, either in the timer mode, the event counting mode

or the pulse width capture mode, bits 7 and 6 of the

Timer Control Register, which are known as the bit pair

TnM1/TnM0, must be set to the required logic levels.

The timer-on bit, which is bit 4 of the Timer Control Reg-

ister and known as TnON, provides the basic on/off con-

trol of the respective timer. Setting the bit high allows the

counter to run, clearing the bit stops the counter. Bits

0~2 of the Timer Control Register determine the division

ratio of the input clock prescaler. The prescaler bit set-

tings have no effect if an external clock source is used. If

the timer is in the event count or pulse width capture

mode, the active transition edge level type is selected by

the logic level of bit 3 of the Timer Control Register

which is known as TnEG. The TnS bit selects the inter-

nal clock source if used.

Timer Mode

In this mode, the Timer/Event Counter can be utilised to

measure fixed time intervals, providing an internal inter-

rupt signal each time the Timer/Event Counter over-

flows. To operate in this mode, the Operating Mode

Select bit pair, TnM1/TnM0, in the Timer Control Regis-

ter must be set to the correct value as shown.

Control Register Operating Mode

Select Bits for the Timer Mode

Bit7 Bit6

In this mode the internal clock is used as the timer clock.

The timer input clock source is either fSYS ,fSYS/4 or the

LXT oscillator. However, this timer clock source is fur-

ther divided by a prescaler, the value of which is deter-

mined by the bits TnPSC2~TnPSC0 in the Timer

Control Register. The timer-on bit, TnON must be set

high to enable the timer to run. Each time an internal

clock high to low transition occurs, the timer increments

by one; when the timer is full and overflows, an interrupt

signal is generated and the timer will reload the value al-

ready loaded into the preload register and continue

counting. A timer overflow condition and corresponding

internal interrupt is one of the wake-up sources, how-

ever, the internal interrupts can be disabled by ensuring

that the ETnI bits of the INTCn register are reset to zero.

Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer TCn pin, can be

recorded by the Timer/Event Counter. To operate in this

mode, the Operating Mode Select bit pair, TnM1/TnM0,

in the Timer Control Register must be set to the correct

value as shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode, the external timer TCn pin, is used as the

Timer/Event Counter clock source, however it is not di-

vided by the internal prescaler. After the other bits in the

Timer Control Register have been setup, the enable bit

TnON, which is bit 4 of the Timer Control Register, can

be set high to enable the Timer/Event Counter to run. If

the Active Edge Select bit, TnEG, which is bit 3 of the

Timer Control Register, is low, the Timer/Event Counter

will increment each time the external timer pin receives

a low to high transition. If the TnEG is high, the counter

will increment each time the external timer pin receives

a high to low transition. When it is full and overflows, an

interrupt signal is generated and the Timer/Event Coun-

ter will reload the value already loaded into the preload

abled by ensuring that the Timer/Event Counter Inter-

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Chart

T i m e r + 2

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Chart (TnEG=1)

HT48R02N Datasheet(PDF) 36 Page - Holtek Semiconductor Inc

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