HT68F03 datasheet(82/139 Pages) HOLTEK

82 / 139 page

HT66F03/HT66F04/HT68F03/HT68F04

Rev. 1.00

April 16, 2010

As the name of the mode suggests, after a comparison

is made, the TM output pin, will change state. The TM

output pin condition however only changes state when

an TnAF or TnBF interrupt request flag is generated af-

ter a compare match occurs from Comparator A or Com-

parator B. The TnPF interrupt request flag, generated

from a compare match from Comparator P, will have no

effect on the TM output pin. The way in which the TM

output pin changes state is determined by the condition

of the TnAIO1 and TnAIO0 bits in the TMnC1 register for

ETM CCRA, and the TnBIO1 and TnBIO0 bits in the

TMnC2 register for ETM CCRB. The TM output pin can

be selected using the TnAIO1, TnAIO0 bits (for the

TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB pins)

to go high, to go low or to toggle from its present condi-

tion when a compare match occurs from Comparator A

or a compare match occurs from Comparator B. The ini-

tial condition of the TM output pin, which is setup after

the TnON bit changes from low to high, is setup using

the TnAOC or TnBOC bit for TPnA or TPnB output pin.

Note that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0

bits are zero then no pin change will take place.

ETM CCRA Compare Match Output Mode

- TnCCLR = 0

Note:

1. With TnCCLR = 0 the Comparator P match will clear the counter

2. TPnA output pin controlled only by TnAF flag

3. Output pin reset to initial state by TnON bit rising edge

HT68F03 Datasheet(PDF) 82 Page - Holtek Semiconductor Inc