ADP4100 datasheet(11/22 Pages) ONSEMI

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ADP4100

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Theory of Operation

The ADP4100 is a 6−Phase VR11.1 regulator. A typical

application circuits is shown in Figure 2.

Startup Sequence

The ADP4100 follows the VR11 startup sequence shown

in Figure 7. After both the EN and UVLO conditions are

met, an internal timer goes through one delay cycle

TD1 (= 2ms). The first six clock cycles of TD2 are blanked

from the PWM outputs and used for phase detection as

explained in the following section. Then the internal

soft−start ramp is enabled (TD2) and the output comes up to

the boot voltage of 1.1V. The voltage is held at 1.1V for the

2 ms, also known as the Boot Hold time or TD3. During TD3

the processor VID pins settle to the required VID code.

When TD3 is over, the ADP4100 reads the VID inputs and

soft−starts either up or down to the final VID voltage (TD4).

After TD4 has been completed and the PWRGD masking

time (equal to VID on the fly masking) is finished, a third

cycle of the internal timer sets the PWRGD blanking (TD5).

Figure 7. System Startup Sequence for VR11

TD1

TD3

TD2

TD5

50ms

TD4

SUPPLY

VTT I/O

(ADP4100 EN)

VCC_CORE

VR READY

(ADP4100 PWRGD)

CPU

VID INPUTS

VID INVALID

VID VALID

VBOOT

(1.1V)

UVLO

THRESHOLD

0.85V

VVID

Figure 8 shows typical startup waveforms for the

ADP4100.

Figure 8. Shows Typical Startup Waveforms for

the ADP4100

Figure 8 typical startup waveforms:

Channel 1: CSREF

Channel 2: PWM1

Channel 3 : Enable

Phase Detection

During startup, the number of operational phases and their

phase relationship is determined by the internal circuitry that

monitors the PWM outputs. Normally, the ADP4100

operates as a 6−Phase PWM controller.

To operate as a 5−Phase Controller connect PWM6 to VCC.

To operate as a 4−Phase Controller connect PWM5 and

PWM6 to VCC.

To operate as a 3−Phase Controller connect PWM4, PWM5

and PWM6 to VCC.

To operate as a 2−Phase Controller connect PWM3, PWM4,

PWM5 and PWM6 to VCC.

To operate as a single phase controller connect PMW2,

PWM3, PWM4, PWM5 and PWM6 to VCC.

Prior to soft−start, while EN is high the PWM6, PWM5,

PWM4 PWM3 and PWM2 pins sink approximately 100

each. An internal comparator checks each pin’s voltage vs.

a threshold of 3.0 V. If the pin is tied to VCC, it is above the

threshold. Otherwise, an internal current sink pulls the pin

to GND, which is below the threshold. PWM1 is low during

the phase detection interval that occurs during the first six

clock cycles of TD2. After this time, if the remaining PWM

outputs are not pulled to VCC, the 100 mA current sink is

removed, and they function as normal PWM outputs. If they

are pulled to VCC, the 100 mA current source is removed, and

the outputs are put into a high impedance state.

The PWM outputs are logic−level devices intended for

driving fast response external gate drivers such as the

ADP3121. Because each phase is monitored independently,

operation approaching 100% duty cycle is possible. In

addition, more than one output can be on at the same time to

allow overlapping phases.

Master Clock Frequency

The clock frequency of the ADP4100 is set with an

external resistor connected from the RT pin to ground. The

frequency follows the graph in Figure 3. To determine the

frequency per phase, the clock is divided by the number of

phases in use. If all phases are in use, divide by 6. If 4 phases

are in use then divide by 4.

(eq. 1)

RT +

fsw

* RTO

Where: CT = 2.2 pF and RTO = 21 K

Output Voltage Differential Sensing

The ADP4100 combines differential sensing with a high

accuracy VID DAC and reference, and a low offset error

amplifier. This maintains a worst−case specification of

±7 mV differential sensing error over its full operating

output voltage and temperature range. The output voltage is

sensed between the FB pin and FBRTN pin. FB is connected

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